Further information on AMD's MACH product line may be found by obtaining (see SUPPORT) the MACH Family Data Book (19829). MACH design assistance is available by obtaining the MACH Technical Briefs Manual (15972) and the MACH Devices Applications Handbook (17020).
Macro PLD Max Max Max Device Pins cells Gates Inputs Outputs Flip-Flops Speed (ns)
MACH 1 Family
MACH110 44 32 900 38 32 32 12, 15, 20 MACH111 44 32 900 38 32 32 7, 10, 12, 15, 20 MACH120 68 48 1200 56 48 48 12, 15, 20 MACH130 84 64 1800 70 64 64 15, 20 MACH131 84 64 1800 70 64 64 7, 10, 12, 15, 20
MACH 2 Family
MACH210 44 64 1800 38 32 64 7, 10, 12, 15, 20 MACHLV210 44 64 1800 38 32 64 12, 15, 20 MACH211 44 64 1800 38 32 64 7, 10, 12, 15, 20 MACH220 68 96 2400 56 48 96 12, 15, 20 MACH221 68 96 2400 56 48 96 7, 10, 12, 15, 20 MACH230 84 128 3600 70 64 128 15, 20 MACH231 84 128 3600 70 64 128 7, 10, 12, 15, 20
Asynchronous MACH Device
MACH215 44 64 1500 38 32 64 12, 15, 20
The MACH (Macro Array CMOS High-density) family provides a new way to implement large logic designs in a programmable logic device. AMD has combined an innovative architecture with advanced electrically-erasable CMOS technology to offer a device with several times the logic capability of the industry's most popular existing PAL device solutions at comparable speed and cost.
Their unique architecture makes these devices ideal for replacing large amounts of TTL, PAL-device, glue, and gate-array logic. They are the first devices to provide such increased functionality with completely predictable, deterministic speed.
The MACH devices consist of PAL blocks interconnected by a programmable switch matrix (Figure 1). Designs that consist of several interconnected functional modules can be efficiently implemented by placing the modules into PAL blocks. Designs that are not as modular can also be readily implemented since the switch matrix provides a high level of connectivity between PAL blocks. The internal arrangement of resources is managed automatically by the design software, so that the designer does not have to be concerned with the logic implementation details.
Figure 1. MACH 1 and 2 Block Diagram
The MACH family consists of the MACH 1 and MACH 2 series of synchronous devices and the MACH215, an asynchronous device. The MACH 1 and 2 series are ideal for synchronous subsystems like memory controllers and peripheral controllers. The MACH215 is appropriate for applications having asynchronous inputs and for collecting random glue logic.
AMD's FusionPLD program allows MACH device designs to be implemented using a wide variety of popular industry-standard design tools. By working closely with the FusionPLD partners, AMD certifies that the tools provide timely, accurate, quality support. This ensures that a designer does not have to buy a completely new set of tools for each new device, but use the tools with which he or she is already familiar. The MACH devices can be programmed on conventional PAL device programmers with appropriate personality and socket adapter modules.
MACH devices are manufactured using AMD's state-of-the-art advanced CMOS electrically-erasable process for high performance and logic density. CMOS EE technology provides 100% testability, reducing both prototype development costs and production costs.
Design tools for MACH devices are widely available both from AMD and from third-party software vendors. AMD supplies MACHXL software as a low-cost baseline tool set and works with tools vendors to ensure broad MACH device support. This allows designers to do MACH device designs using the same tools that they would use to do PAL device designs, whether it is MACHXL software or any of the other popular PLD device design packages.
Design entry is the same as that used for PAL devices. The basic logic processing steps are the same steps that are needed to process and minimize logic for any PAL device. Simulation is available for verifying the correct behavior of the device. Functional (unit-delay) simulation of MACH devices is supported in all approved software packages, and other options for simulating the timing and board-level behavior of the MACH devices are available. The end result is a JEDEC file that can be downloaded to a programmer for device configuration.
MACH device design methodology differs somewhat from that of a PAL device due to the automatic design fitting procedure that the software performs. Designs written by logic designers--whether by schematic capture, state machine equations, or Boolean equations--are partitioned and placed into the PAL blocks of the MACH device. While this procedure is handled automatically by the software, the software can also accept manual direction based upon the user's working knowledge of the design. MACH device connectivity is 100% with the exception of the MACH230. This facilitates automatic place and route.
AMD, the AMD logo and MACH are registered trademarks and FusionPLD is a service mark of Advanced Micro Devices, Inc.